FIG. 1 illustrates the pattern of a transfer transistor unit installed in a row decoder of a conventional NAND-type flash memory. A transfer transistor transmits a wordline enable signal corresponding to a wordline address and a selection gate enable signal to a block selected from a memory cell array. To simplify the drawing and explanation, a case where there are 8 transfer transistors will be described.
The transfer transistor unit includes transfer transistors Q0 through Q7 to transmit the wordline enable signal to wordlines WL0 through WL7. Each transfer transistor is an NMOS transistor formed on a p-type substrate and is structured such that a source/drain region has a satisfactory resistance against a program voltage and an erase voltage.
Referring to FIG. 1, during a program operation, a threshold voltage of a transfer transistor, i.e., 20+Vth, for example, 22 V, is applied to the gates of the transfer transistors Q0 through Q7. As a result, 20 V is applied to a selected wordline among the wordlines WL0 through WL7. In addition, 0 V is applied to non-selected wordlines adjacent to the selected wordline and 10 V is applied to the other non-selected wordlines.
The lower portions of the transfer transistors Q0 through Q3 are arranged in order of CG1 (WL1), CG3 (WL3), CG0 (WL0), and CG2 (WL2), and therefore, a potential difference between the transfer transistors Q1, Q3, Q0, and Q2 adjacent each other in X directions (i.e., X1, X2, and X3) is suppressed to 10 V. In addition, the upper portions of the transfer transistors Q4 through Q7 are arranged in order of CG5 (WL5), CG7 (WL7), CG4 (WL4), and CG6 (WL6), and therefore, a potential difference between the transfer transistors Q5, Q7, Q4, and Q6 adjacent each other in the X directions X1, X2, and X3 is suppressed to 10 V. Further, a potential difference between the transfer transistors Q0 and Q4, and Q3 and Q7, adjacent each other in Y directions (i.e., Y1, Y2, Y3, and Y4) is suppressed to 10 V.
In order to prevent current from leaking due to the potential difference described above, the arrangement of transfer transistors in the transfer transistor unit can be controlled so that a distance between the transfer transistors is optimized. However, a transfer transistor for driving a select transistor is different from a transfer transistor for driving a wordline, and therefore, a distance therebetween may be different.